Building a 6800 CPU on an FPGA with nMigen (part 1)

TinyFPGA BX ([1]) and nmigen/yosys as the fully open source toolchain for generating logic with Python and formally verifying it ([2], [3]). There is a good nMigen tutorial by Robert Baruch ([4]. [5]). Alternatively, if you really want to try Verilog first (not a bad idea), I enjoyed reading a book "Designing Video Game Hardware in Verilog" ([6]). 1. [link] 2. [link] 3. [link] 4. [link] 5. ▶ this video 6. [link]

in “Awesome Lattice FPGA Boards” · View on HN

Robert Baruch on Youtube is building a RISC-V CPU core of comparable complexity to the one in the OP using nMigen which is an HDL based on Python and it looks like a very nice tool to work with relative to other HDLs I've seen (though I've never had to actually use an HDL myself before so I may not be the best judge). Here's a playlist of the video series, with the earlier videos basically being an introduction to nMigen: [link] He's got another series that's focused more on the HDL itself building a (relatively much simpler) 6800 CPU core: ▶ this video

in “Lion: A formally verified, 5-stage pipeline RISC-V core” · View on HN

nMigen is pretty cool and capable. I can only recommend these Youtube series, where nMigen is used to build a full 6800 CPU: ▶ this video

in “Glasgow: Scots Army Knife for Electronics” · View on HN

Semi-related, I've been enjoying Robert Baruch's videos[1] on creating a FPGA implementation of the 6800, using nMigen and formal verification. First videos are almost like live coding, then he skips to a more compact format. As a regular programmer, it's quite interesting to get into how the bits actually end up getting the work done. [1]: ▶ this video

in “Show HN: 1.5kb Microkernel for Ben Eater's 6502 Computer” · View on HN