The Mill CPU Architecture – The Compiler (10 of 13) on HackerTube: recommended by 1 Hacker News commenter across 1 month, 2015–2023.
lecture · advanced · evergreen
A long Mill Computing lecture on the Mill CPU's compiler toolchain, covering the specializer that targets family members, scheduling and latency passes, and the belt. It explains how the compiler handles a wide-issue, exposed-pipeline design.
Cited as the authoritative source on how Mill's VLIW-style compiler specializes code and differs from Itanium.
“have a design talk that covers these concepts wonderfully in the general form”
3 Hacker News comments link this video. Each one links back to its thread.
The (disconcertingly silent) Mill CPU company have a design talk that covers these concepts wonderfully in the general form, while explaining their various innovations. e.g. this video describes how their VLIW compiler does partial compilation/'specialisation' to allow the same input to be consumed on machines with different variations of hardware features. ▶ this video
in “Ask HN: Why did stack-based CPUs lose out?” · View on HN
It's been too long since I watched the videos, so unfortunately I don't remember the specifics. For reference, here's[1] the relevant one on the compiler aspect. I do seem to recall that they seemingly had studied the failures of Itanium, and supposedly designed their architecture to not fall into the same pitfalls as with the EPIC/Itanium. One aspect I recall is that while they have VLIW, different operations within the (compound) instruction are issued in such a way that lets them be interdependent. Like, a single VLIW instruction could have an add and a multiply, where the result of the add is used as input for the multiplication. So while the operations are grouped in a single instruction, they're not executed strictly in parallel. There's a lot of other aspects too, that's just the one I remember. But yeah, really curious to know how that pudding will turn out. [1]: ▶ this video
in “SIMD Instructions Considered Harmful (2017)” · View on HN
The answer at 1:26:12 [1] about the belt being in fact a 'proxy' of the bypass network is very interesting. [1] ▶ this video
in “The Mill CPU Architecture – The Compiler [video]” · View on HN