Experiences Building Edge TPU with Chisel

Google had a really interesting talk on their experiences with Chisel in designing the first Edge TPU chip. A lot of the issues are specific to industrial chip design, where verification and coverage are essential, but many would apply to small-scale personal designs as well. A good overview of the advantages as well as the problems. And many of the problems would apply to other front ends, which are essentially using Verilog as the target language. ▶ this video

in “Ask HN: Choice of HDL for an FPGA Project” · View on HN

Google TPU engineers used open-source Chisel for ASIC design (2018), ▶ this video "Google Edge TPU devices" , 100 comments (2019), [link] & [link] "Coral Edge TPU review" , 100 comments (2020), [link] "TPU transformation: 10 years of our AI-specialized chips" , 60 comments (2024), [link]

in “OpenTPU: Open-Source Reimplementation of Google Tensor Processing Unit (TPU)” · View on HN

It was in fact the EdgeTPU (which is different from the TPU used in data centers). The talk from a google engineer can be found on youtube: ▶ this video Please note that they were using a version of Chisel from 5+ years ago and many things have changed since then. It is still true though that Chisel can be hard to learn for typical hardware engineers, which is why it may be best suited for small and highly dedicated teams rather then large hardware companies. [EDIT] Here is a talk from a solo-developer using the latest version of Chisel: [link]

in “Chisel/FIRRTL Hardware Compiler Framework” · View on HN

Google built one of their TPUs in Chisel [1]. TL;DW: Chisel is beautiful/fun to write in, with a definite productivity bonus, but has a pretty large learning curve and had a much greater verification cost, partly because it's an HLS (most have that problem) and also lack of any tooling. Both of those costs are gradually being reduced (though in my opinion, not enough to not make verification a PITA). [1] ▶ this video

in “An Open-Source FPGA-Optimized Out-of-Order RISC-V Soft Processor (2019) [pdf]” · View on HN

In Nov 2018, Google engineers who designed the TPU gave a presentation about the use of open-source Chisel for designing the ASIC, ▶ this video From [link] > Google will have the cloud TPU ... to handle training models for various machine learning-driven tasks, and then run the inference from that model on a specialized chip that runs a lighter version of TensorFlow that doesn’t consume as much power ... dramatically reduce the footprint required in a device that’s actually capturing the data ... Google will be releasing the chip on a kind of modular board not so dissimilar to the Raspberry Pi ... it’ll help entice developers who are already working with TensorFlow as their primary machine learning framework with the idea of a chip that’ll run those models even faster and more efficiently.

in “Google Edge TPU Devices” · View on HN